1. Field of the Invention
The present invention relates to a three dimensional stacked nonvolatile semiconductor memory.
2. Description of the Related Art
BiCS (Bit Cost Scalable) technology is known as a technology for suppressing a bit cost of a semiconductor memory by increasing the capacity thereof by a three dimensional structure (refer to, for example, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory” 2007 Symposium on VLSI Technology Digest of Technical Papers. p. 14).
A nonvolatile semiconductor memory to which the BiCS technology is applied (hereinafter, called a BiCS memory) has a feature in that it not only has a three dimensional structure but makes bit cost scalability possible so that a bit cost can be reduced in proportion to an increase of the number of stacked layers by devising a device structure and a process technology.
In, for example, a NAND flash memory to which the BiCS technology is applied (hereinafter, called a BiCS-NAND flash memory), a memory capacity, which greatly exceeds the limit of the memory capacity of a NAND flash memory having a two-dimensional structure, can be realized by increasing the number of cells in a longitudinal direction which comprise a NAND column by increasing the number of stacked layers.
However, since the BiCS memory which is represented by a BiCS-NAND flash memory has a unique device structure, there are many problems to be solved to practically use the BiCS memory.
A read disturb is exemplified as one of the problems.
The BiCS memory has such a feature that cell units are included in one block connected to one bit line. Further, the cell units cannot be selected at the same time from the viewpoint of a circuit operation. Accordingly, a non-selected cell unit which does not include a memory cell to be read exists in a selected block.
This problem does not occur in a flash memory having a two-dimensional structure.
Therefore, read disturb must be examined to prevent variation of a threshold voltage of a memory cell in a non-selected cell unit in a selected block in read.
In particular, in the BiCS memory, since it is not necessary to apply a read potential and a transfer potential to the cell unit in the non-selected block unlike the flash memory having the two-dimensional structure, it is not necessary to examine read disturb to the cell unit in the non-selected block. However, when a read potential is applied to a non-selected memory cell because a non-selected cell unit in a selected block is cut off from a bit line, a threshold voltage is varied in a non-selected memory cell existing nearer to the bit line side than the above non-selected memory cell by read disturb depending on the state of a threshold voltage of the non-selected memory cell to which the read potential is applied.